//*******************************************************************       //
//IMPORTANT NOTICE                                                          //
//================                                                          //
//Copyright Mentor Graphics Corporation 1996 - 1999.  All rights reserved.  //
//This file and associated deliverables are the trade secrets,              //
//confidential information and copyrighted works of Mentor Graphics         //
//Corporation and its licensors and are subject to your license agreement   //
//with Mentor Graphics Corporation.                                         //
//                                                                          //
//Use of these deliverables for the purpose of making silicon from an IC    //
//design is limited to the terms and conditions of your license agreement   //
//with Mentor Graphics If you have further questions please contact Mentor  //
//Graphics Customer Support.                                                //
//                                                                          //
//This Mentor Graphics core (m8051w v2002.080) was extracted on             //
//workstation hostid 8316cbec Inventra                                      //
// Dual-port RAM model for M8051W/EW internal data memory
// 
// $Log: ram.v,v $
// Revision 1.5  2001/11/20
// First checkin of version 2 features and name change
//
// Revision 1.1  2001/11/14
// First EW checkin
//
// Revision 1.4  2000/03/06
// Revised configuration scheme
//
// Revision 1.3  2000/02/05
// Name change from m8051e to m8051ewarp
//
// Revision 1.2  2000/01/05
// Test bench updates, wait generator moved to separate module.
//
// Revision 1.1.1.1  1999/10/28
// "initialization and source check-in for m8051e"
//
//
////////////////////////////////////////////////////////////////////////////////
//
// Purpose      :       Configurable number of 8-bit flip-flops for modelling
//              :       internal memory used by the M8051W/EW Soft Core.
//
////////////////////////////////////////////////////////////////////////////////

`include "m8051w_tb_cfg.v"

module ram (CSN1, CSN2, RWN1, RWN2, A1, A2, DI1, DI2, DO1, DO2, TRESET, CLK);
//*******************************************************************       //
//IMPORTANT NOTICE                                                          //
//================                                                          //
//Copyright Mentor Graphics Corporation 1996 - 1999.  All rights reserved.  //
//This file and associated deliverables are the trade secrets,              //
//confidential information and copyrighted works of Mentor Graphics         //
//Corporation and its licensors and are subject to your license agreement   //
//with Mentor Graphics Corporation.                                         //
//                                                                          //
//Use of these deliverables for the purpose of making silicon from an IC    //
//design is limited to the terms and conditions of your license agreement   //
//with Mentor Graphics If you have further questions please contact Mentor  //
//Graphics Customer Support.                                                //
//                                                                          //
//This Mentor Graphics core (m8051w v2002.080) was extracted on             //
//workstation hostid 8316cbec Inventra                                      //

parameter RAM_SIZE = 256;
parameter RAM_AWIDTH = 8;
parameter T_ACCESS = 5;
parameter T_W_PROPN = 5;

output [7:0] DO1,DO2;                       // data out
input  [7:0] DI1,DI2;                       // data in
input  [RAM_AWIDTH-1:0] A1, A2;             // address
input  RWN1, RWN2;                          // high for read, low for write
input  CSN1, CSN2;                          // active-low chip-select
input  TRESET;                              // test reset to initialise data
input  CLK;                                 // flip-flop clock input

reg    [7:0] mem[0:RAM_SIZE-1];             // the memory array
reg    [7:0] DO2;
wire   [7:0] DO1;
wire   [RAM_AWIDTH-1:0] A1_internal;

// synopsys translate_off

integer i;


// RAM access time constants

parameter Twwdo = `Tiramwwdo;                         // read access time
parameter Taa   = `Tiramacc;                          // write propagation delay

// Optional set up and hold checks for gate-level simulation
`ifdef GATE_LEVEL
specify

specparam Tasw = `Tiramasw;                           // address set up
specparam Tah  = `Tiramah;                            // address hold
specparam Tdw  = `Tiramdw;                            // data set up
specparam Tdh  = `Tiramdh;                            // data hold

$setup(A2, negedge CLK , Tasw);
$hold(posedge CLK , A2, Tah);
$setuphold(posedge CLK , DI2, Tdw, Tdh); 

endspecify
`endif

// Initialise array for ease of simulation (avoids X-propagation).
initial
  for (i=0; i < `IramSize; i = i +1)
    mem[i] <= 8'h00;

// synopsys translate_on

// simulate read data output delay on data write
always @(posedge CLK  or posedge TRESET)
  if (~CSN2 && ~RWN2)
    mem[A2] <= #T_W_PROPN DI2;
  
// simulate read access time delay
assign #T_ACCESS A1_internal = A1;

assign DO1 = CSN1? `BadData: mem[A1_internal];

endmodule
